The principle way of reducing contact resistance between polysilicon gates and source/drain regions and interconnect lines is by forming a metal silicide atop the source/drain regions and the gate electrodes prior to application of the conductive film for formation of the various conductive interconnect lines. Presently, the most common metal silicide materials are CoSi2 and TiSi2, typically formed by the so called salicide (self-aligned silicide) process. In the salicide process, a thin layer of a metal, such as titanium, is blanket deposited over the semiconductor substrate, specifically over exposed source/drain and gate electrode regions. The wafer is then subjected to one or more annealing steps, for example at a temperature of 800° C. or higher for titanium. This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrodes, thereby forming a metal silicide (e.g., TiSi2). The process is referred to as the self-aligned silicide process because the silicide layer is formed only where the metal material directly contacts the silicon source/drain regions and the polycrystalline silicon (polysilicon) gate electrode. Following the formation of the silicide layer, the unreacted metal is removed and an interconnect process is performed to provide conductive paths, such as by forming via holes through a deposited interlayer dielectric and filling the via holes with a conductive material, e.g., tungsten.
The thickness of the silicide layer is an important parameter because a thin silicide layer is more resistive than a thicker silicide layer of the same material. Therefore, a thicker silicide layer increases semiconductor speed. The formation of a thick silicide layer, however, may cause a high junction leakage current and low reliability, particularly when forming ultra-shallow junctions. The formation of a thick silicide layer consumes silicon from the underlying semiconductor substrate such that the thick silicide layer approaches and even shorts the ultra-shallow junction, thereby generating a high junction leakage current.
It is desirable to also lower the resistance of the gate electrode to increase the speed of the device. The greater the amount of silicon converted into silicide in the gate electrode, the lower the resistance will be in the gate electrode. However, formation of silicide on the gate electrode simultaneously with the source/drain regions leads to the risk of spiking in the source/drain regions if the complete silicidation of the gate electrode is attempted. This process, therefore, suffers from a very narrow processing window due to the strong likelihood that exposure of the metal and silicon to rapid thermal annealing conditions sufficient to completely silicidize a gate electrode will also cause the silicide in the source/drain region to spike and reach the bottom of the junction, undesirably causing leakage.
Various methods have been suggested for forming fully silicided gate electrodes. For example, B. Tavel et al. propose in “Totally Silicided (CoSi2) Polysilicon: a novel approach to very low-resistive gate (˜2 Ω/sq) without metal CMP nor etching” (IEDM 01-825) (IEEE 2001) formation of a fully silicided gate electrode by the following steps: (a) polysilicon gate electrode formation; (b) simultaneous silicidation of the source/drain and gate area, with the gate only partially silicided with a Cobalt/Titanium silicide; (c) deposition of a nitride liner; (d) deposition of a dielectric coating layer over the nitride liner; (e) chemical mechanical polishing (CMP) the dielectric and liner layers to the top surface of the gate electrode; (f) deposition of a second Cobalt/Titanium layer over the polished dielectric layer and exposed gate structure; and (g) silicidation of the remaining portion of the gate electrode.
While the method of Tavel et al. provides a fully silicided gate electrode, it is very difficult to control the gate electrode height when a CMP step is employed. For example, the polishing rate is different at the wafer center and the wafer edge. Further, the CMP process tends to result in dishing and erosion, leaving concave gate top surfaces, i.e., individual gates with non-uniform heights. Because the gate electrode height is difficult to control, i.e., each wafer may include gates having different heights and individual gates may have non-uniform heights, control of the complete silicidation of the gate electrodes is also difficult. Further, if the gate heights are too low, bridging may occur between the gates and active regions. Still further, the device speed is very difficult to control by this method.
Therefore, there remains a need for a method of increasing silicide thickness at the gate area and fully silicidizing a gate electrode, such as a method that affords greater control over the gate electrode height.